Hypercomputer's External I/O Capabilities
A new market trend for reconfigurable computing is emerging, and Starbridge Systems is positioned squarely in its path. Because of a unique and market leading architecture, Starbridge Hypercomputing becomes the perfect tool for high-end test data computing.
 Industry Challenges
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The trend toward serial links and away from parallel links boosts speeds but also adds complexity and testing challenges. With stable, and even shrinking prices, the fully loaded cost of testing cannot increase.
High-speed interfaces such as Serial ATA, HyperTransport, Rapid I/O, InfiniBand and PCI Express are becoming pervasive in computers and networking equipment. Speeds today range from 1.5 - 3 Gbit/s and in the very near future will reach 6.4 Gbit/s and beyond as new technologies are developed and deployed. Meanwhile the price of these products continues to drop. Historically, higher levels of fault coverage, and testing at high speed, have driven up cost-of-test (COT). But now more than ever, to stay competitive, manufacturers must have a low cost, high integrity test solution for high volume device manufacturing. System flexibility and re-use become critical elements in the decision.
In spite of these advances in I/O capabilities, there are still many grand-challenge test scenarios where the data size and speed requirements outstrip these current I/O capabilities by orders of magnitude. Thus, the challenge still remains as to how to keep up with the higher data resolutions and meet customer requirements.
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Reconfigurable Hypercomputing Solution
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What is needed is a testing solution that can meet design validation requirements and can easily adapt to address the challenges of high volume testing. Most importantly, with a reconfigurable platform, you can remove time and resources that it would normally cost to design your own system. Starbridge addresses a variety of challenges, all from a reconfigurable platform architectural approach. Take this one, and run with it!
The Starbridge reconfigurable Hypercomputer with the Viva development environment offer a wide array of benefits that represent a new and leading edge approach to the challenges of an ever-evolving test market:
External I/O bandwidth – The HC-62 has 552 lines at 133 Mbits/sec each.
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Benefit:
"Pain Relief" and "Profit" - minimizes the system design requirements, and gives a flexible ability to bring in high-speed data feeds from a myriad of devices.
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Bus bandwidth – Data transfer rate from the FPGA board to the host through the PCIX interface. The HC-62 has bus bandwidth speeds of 60 Mbytes/sec on reads, and 220 Mbytes/sec on writes.
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Benefit:
"Pain Relief" enables normalized data to be quickly moved to the host for video processing.
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Memory Size – The HC-62 comes with 18 to 36 Gigabytes of tightly coupled DRAM in local proximity to the FPGA based processing elements.
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Benefit:
"Pain Relief" and "Profit" - saves on execution time, enabling more parallel processing to happen on more data per clock cycle.
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Sensor Testing – requires being able to handle large amounts of real time data. This data is of variable precision and formats based on customer requirements.
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Benefit:
"Pain Relief" and "Profit" - a reconfigurable, programmable front end minimizes the engineering investment and turn around time for data normalization, yielding higher utilization and overall ROI of the system.
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Memory Bandwidth – The HC-62 has tightly coupled DRAM to each processing element, with four 64-bit parallel memory channels on each PE.
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Benefit:
"Pain Relief" and "Profit" - this architecture reduces memory latency, and speeds up the overall performance of many types of applications.
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High-Speed Data Acquisition – Many high-end test environments need a system that can interface with data acquisition front ends from two perspectives: speed, and programmability. This is one of the leading requirements. The Hypercomputer offers 552 lines for high-speed data acquisition, and offers the user the ability to configure and use those lines however they wish to.
Plenty of Memory – Industrial strength test fixtures need systems with large amounts of on-board memory, preferably over 100 GBytes. The need for memory is based on the need to eliminate legacy bottlenecks in today’s existing systems. Moving the problem space into a large-scale reconfigurable substrate with sufficient memory enables massive parallel computation that has heretofore been impossible to obtain.
Functionality Growth – High-end test environments need a system with the potential to grow in functionality … that is, where more of the overall system level functionality can be migrated off of legacy hardware onto the reconfigurable portion of the system over time in order to gain a greater overall ROI over time.
Flexible Platform – The reconfigurable nature of the machine, with a standard programming interface saves time and money. Often times, test fixtures and test stations are constructed on a per-job basis, and many times they can’t be re-used. Using lower end Hypercomputers, offers the premise and promise that a Hypercomputer with VIVA holds for the next generation test station platform.
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Benefit:
"Profitability" - This level of flexibility and re-use offers a strong ROI benefit.
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HC-62 Board Specifications
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Eleven Virtex-II FPGAs on the board assembly (~62 million gates)
Tightly-coupled Memory
• 36 Gigabytes DDR DRAM memory
• Memory bandwidth: 38 Gigabytes/sec
• 36 64-bit parallel memory channels per board
• 3 Megabytes cache memory (324 Kilobytes per FPGA)
