And now, Starbridge Systems introduces the new Hypercomputer that provides the next level of High Performance Computing in a Hybrid Computer System. The system integrates cluster computing into the FPGA, not FPGAs into the cluster. This integrates FPGAs in a unique architecture to provide a combination of Linux cluster computing tightly coupled with highly parallel FPGA fabric. This concept achieves the highest level of heterogeneous computing with the tightly coupled integration of serial processors and FPGAs. Legacy C or Fortran code can be easily profiled to find those areas of compute intensive algorithms to be programmed through Viva to run in FPGA fabric and achieve extreme acceleration in computation time. Vector computing, cluster computing, reconfigurable computing, mix and match for your customized hardware/software performance enhanced system.

Memory bandwidth problems are greatly reduced with 72 independent memory channels of 1 G Byte or 2 G Byte memory capacity per channel. I/O bandwidth is solved with 144 high-speed I/O interfaces that can be programmed for customized or industry standard I/O protocols. Interfaces such as Infiniband, PCI Express, Fibre Channel, Serial Rapid I/O, Gigabit Ethernet channels and other industry standard protocols can be programmed for interfacing with SANS storage, or other methods of data storage, high speed I/O and other peripheral communications. 72 SATA hard drives provide over 20 Terabytes of parallel disk storage.

What is Hybrid Computing?
Imagine a computing solution that takes advantage of the flexibility of a microprocessor and the speed of parallel computing with FPGA hardware. By using microprocessors in parallel with FPGA hardware processing you have the ability of optimizing your code to utililze the strengths of each. In so doing you can exponentially accelerate the execution speed of your application. This is Hybrid Computing.

Why Hasn’t the Hybrid Model Been Successful?
Until recently the prospects of hybrid computing have not been promising. Previous methods for hybrid computing have leveraged microprocessors interfaced through external bus interfaces to connect to an FPGA. Many of the benefits gained through FPGA acceleration were lost in the delay created by the link between the two processing methods. While both the software (processor) side and the hardware (FPGA) side of the application were running at respectable rates, the latency of the data passing from one design to the other creates a bottleneck that hinders performance of the results.

Why Now?
Today, with the processor embedded in the FPGA, it is tightly coupled to the FPGA fabric. The latency between the processor and the FPGA design is eliminated. The benefits of both worlds can now be combined in a single design. By analyzing the code for inherently parallel segments or by profiling the code to determine the computationally intensive portions, you can extract sections of code from the software and implement these algorithms in hardware on the FPGA. The hardware combined with the software implementation will greatly increase efficiency while reducing delay.

Is the Transition Difficult?
Now instead of recreating your secret sauce from the ground-up in hardware, your code will remain largely intact, with only key components or algorithms implemented in hardware.

Viva the key ingredient
Parallel processing using hybrid computing is easy with Viva. Viva’s library of microprocessors allows you to perform microprocessing and FPGA hardware processing in parallel on an FPGA. You are able to perform true parallel processing within a single chip. Even better, using Viva to perform hybrid computing allows you to take advantage of hardware execution speed in parallel by transferring computationally intensive functions directly onto the FPGA fabric.

A Viva FPGA hardware design is parallel by nature, but microprocessors are serial. A microprocessor embedded in an FPGA, with a parallel subroutine designed in Viva and implemented in FPGA fabric, can provide accelerated computing. The microprocessor will issue an instruction to the FPGA fabric. The FPGA will execute the subroutine in parallel, returning the results on a subsequent processor instruction. Using Viva to perform parallel processing in this manner is an easy way to obtain optimal application performance.

The next generation of Hypercomputer:
4 U Configuration
72 Power PCs running Linux (48,600 DMIPS)
72 node Linux Cluster with tightly coupled FPGA fabric
144 I/O channels for high-speed interfaces(936Gb/s)
72 SATA disk drives(21 TBytes, 60Gb/s peak, 28 Gb/s sustained)
72 Parallel Memory channels
36 G Bytes to 72 G Bytes DRAM
Viva integrated Power PC/FPGA fabric interface
Linux OS
Scaleable and expandable
Legacy C/Fortran Code with FPGA parallelism acceleration