Design: Implementation Independent Algorithm Description Language |
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The Viva algorithm editor allows the purest expression of any numerical method. It is an object oriented, graphical, recursive expression mechanism manifested as a graphical drag and drop design tool. By "Implementation Independent" it is meant that your algorithms are designed regardless of the physical architecture of the final targeted run environment. With traditional programming languages, your algorithm must be decomposed to adhere to the constraints of the serial language lexicon by a language compiler. The languages themselves mimic the constraints of the hardware that they target by forcing such expression constraints as fixed data types, and serial execution expression in order to accommodate the microprocessor based execution system.
In the past couple of years, attempts have been made to accommodate the growing need for system and application level hardware programming on today's more sophisticated FPGAs. One approach is to extend the abstraction level of standard hardware design languages such as Verilog. This is somewhat useful in the EDA space, but doesn't lend itself to traditional application programmers attempting to create applications for HPC. Another more common approach, especially in the reconfigurable high-performance computing (HPC) world, is to extend the functionality of C++ with templates for programming parallelisms into hardware. There are several offerings in this model, some better than others. As these approaches become closer to standard C, there is a loss in the amount of power and efficiency that can be exploited it the FPGAs.
Viva was designed from the beginning with scalable FPGA programming in mind, enabling you to express your algorithm with all of its natural parallelisms and recursive expressions in an object oriented, graphical environment. By dragging functional objects onto a design pallet called a sheet, and connecting them together with transports that represent the data flow, you can easily model your algorithm, capturing all of its inherent parallelisms. In Viva, because the default design expression is parallel, serial execution is expressed by exception. Objects are "polymorphic" and can be used with different data types, data rates, and data precisions, thus offering code re-use benefits. This enables the designer to negotiate design requirement trade-offs between time (how many clock cycles must I execute in) and space (how many hardware resources can I afford to use for this operation). In Viva, you have the freedom to design right down to the gate level of expression, or create much higher-level objects that represent system level abstractions. Viva ships with math libraries, and many other objects for facilitating the algorithm development process.
Viva will ultimately build a custom architecture for your algorithm right in the reconfigurable hardware based on its expression, and the capacity and capabilities of the target system. As you consider specific design and data flow requirements, you can deterministically mix and match archetypes, objects, and design approaches as needed. Viva enables "architecture on demand" and enables you to create optimal implementations of your algorithms in hardware.
For more information, or for a supported Viva test drive, please contact the Starbridge sales department at 801-984-444, or email us at: sales@starbridgesystems.com.
