Design: Algorithm Independent Architecture Description Language |
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Another aspect of Viva is its ability to capture and abstract the target hardware systems from the algorithm designer. Viva takes the virtual machine concepts of Java, which facilitates code written on one computer to execute on other computers, to a higher level of abstraction. This new abstraction is organized around the idea of a system description that incorporates the behavioral capabilities of the system, the resources consumed by behaviors, and the costs associated with resources. System descriptions are created and combined hierarchically to define the overall target system or execution environment that the user programs operate in.
In the system editor, Viva is able to describe the physical components of the data processing partition candidates. This can be anything from Field Programmable Gate Arrays, memories, busses, I/O interfaces, microprocessors, ASICs, and communication and behavioral systems. The physical components, their behaviors, timings, and costs are all captured within Viva. All of the available resources described in a VIVA "System Description" become partition candidates for computational data processing. These can be deterministically assigned by the algorithm designer, or can be assigned, partitioned, and negotiated by Viva itself. Thus, any type of system including CPU's, FPGA's, and communication systems and any permutation or combination thereof can be modeled in Viva enabling user programs to execute on any compute substrate transparently … and Viva accomplishes this without the overhead of an interpreted execution layer.
System Descriptions in Viva exist for the X-86 system for use on a PC in simulating your design. They also exist not only for the Starbridge line of Hypercomputers, but also for:
The Honeywell Reconfigurable Space Computer
The XESS XSB-300 Board
The XESS XSV Board
The Smiths-Aerospace PMC Board
The SGI Reconfigurable hardware system
Others in Progress, including major reconfigurable HPC vendors
This aspect of Viva allows for the ability to target your algorithm source code to different execution environments without changing your code. If the algorithm has been designed properly (no explicit hard coded hardware dependencies), swapping in a different system description and recompiling (solving) is all that is required for execution on a different target system. Viva uses the system description as context for the synthesis operation, resulting in a compiled program that resolves into the machine description. The benefit of "Future-Proofing" your code for yet-to-be developed hardware becomes obvious.
Starbridge Hypercomputers contain large numbers of high density FPGAs, with many Gigabytes of tightly coupled dram. Because this hardware is reconfigurable, and all of the capabilities, communications systems, and behavioral systems are understood by Viva, it can be optimized for a myriad of different algorithms and numerical methods. The same piece of hardware can literally be utilized as custom hardware architecture, optimally designed to maximize the performance of your algorithm.
Note – There are different architectural approaches taken by the many FPGA board and system vendors. All are good, and offer an array of differences based on specific application needs. Viva can facilitate all of them. Some leverage their strong capabilities for streaming data through the FPGA system, using the FPGA as a co-processor and offloading code execution from the microprocessors. The Starbridge Hypercomputer is designed as a very dense and "balanced" system, enabling the FPGAs to act not as coprocessors, but as primary processing elements. Gigabytes of tightly coupled DRAM are distributed around each FPGA, offering extremely high on-board communications bandwidth between FPGAs and memory, thus offering a powerful, balanced computing environment with minimal latency.
For more information, or for a supported Viva test drive, please contact the Starbridge sales department at 801-984-444, or email us at: sales@starbridgesystems.com.
